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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 17 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 17 Page - ATMEL Corporation |
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17 / 282 page  17 7728D–AVR–07/09 ATtiny87/ATtiny167 Figure 3-2. Data Memory Map 3.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 3-3. Figure 3-3. On-chip Data SRAM Access Cycles 3.3 EEPROM Data Memory The ATtiny87/167 contains EEPROM memory (see “E2 size” in Table 3-1 on page 15). It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register. Section 21. “Memory Programming” on page 225 contains a detailed description on EEPROM programming in SPI or Parallel Programming mode. 32 Registers 64 I/O Registers Internal SRAM (ISRAM size) 0x0000 - 0x001F 0x0020 - 0x005F ISRAM end 0x0060 - 0x00FF Data Memory 160 Ext I/O Reg. ISRAM start clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address CPU Memory Access Instruction Next Instruction |
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