ATtiny167-ESSZ datasheet(69/282 Pages) ATMEL

69 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

9.2.2

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port.

9.2.3

Break-Before-Make Switching

In the Break-Before-Make mode when switching the DDRxn bit from input to output an imme-

diate tri-state period lasting one system clock cycle is introduced as indicated in Figure 9-3.

For example, if the system clock is 4 MHz and the DDRxn is written to make an output, the

immediate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the

port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is

two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the

port-wise BBMx enable bits. For further information about the BBMx bits, see “Port Control

no immediate tri-state period introduced.

Figure 9-3.

Break Before Make, switching between input and output

9.2.4

Switching Between Input and Output

When switchin g be tween tr i-sta t e ({DDxn , PORTxn } = 0, 0) a nd o u t put high

({ DDxn, P O R Txn} = 1 , 1 ), an int e rmed i a t e sta t e with e i t her pull-up e nabled

{DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the

pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the

difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the

MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the

port.

Switching between input with pull-up and output low generates the same problem. The user

must use e i ther the t r i-state ({DDxn, PORTxn} = 0, 0) or t h e output high state

({DDxn, PORTxn} = 1, 1) as an intermediate step.

tri-state

0x02

0x01

0x55

nop

immediate tri-state cycle

out DDRx, r16

YSTEM CLOCK

R 16

R 17

NSTRUCTIONS

PORTx

DDRx

Px0

Px1

out DDRx, r17

immediate tri-state cycle

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