ATtiny167-ESSZ datasheet(91/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

The OCR0A Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the

double buffering is disabled. The double buffering synchronizes the update of the OCR0A

Compare Register to either top or bottom of the counting sequence. The synchronization pre-

vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output

glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buff-

ering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is

disabled the CPU will access the OCR0A directly.

10.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced

by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not

set the OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real com-

pare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set,

cleared or toggled).

10.5.2

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occurs in

the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be

initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter

clock is enabled.

10.5.3

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer

clock cycle, there are risks involved when changing TCNT0 when using the Output Compare

channel, independently of whether the Timer/Counter is running or not. If the value written to

TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect

waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the

counter is downcounting.

The setup of the OC0A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-

pare (FOC0A) strobe bit in Normal mode. The OC0A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value.

Changing the COM0A1:0 bits will take effect immediately.

10.6

Compare Match Output Unit

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator

uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare

match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 10-4 shows a

simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O

bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control

registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring

to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin.

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