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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 52 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 52 Page - ATMEL Corporation |
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52 / 282 page  52 7728D–AVR–07/09 ATtiny87/ATtiny167 Figure 6-5. Brown-out Reset During Operation 6.1.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 53 for details on operation of the Watchdog Timer. Figure 6-6. Watchdog System Reset During Operation 6.1.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATtiny87/167, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. VCC RESET TIME-OUT INTERNAL RESET VBOT- VBOT+ tTOUT CK CC Bit 7 6 543210 – – – – WDRF BORF EXTRF PORF MCUSR Read/Write RRRR R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description |
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