ATtiny167-ESSZ datasheet(65/282 Pages) ATMEL

65 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

• Bit 1 - PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

• Bit 0 - PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0

Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

8.3.5

Pin Change Interrupt Flag Register – PCIFR

• Bit 7, 2 – Res: Reserved Bits

These bits are unused bits in the ATtiny87/167, and will always read as zero.

• Bit 1 - PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 0 - PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

8.3.6

Pin Change Mask Register 1 – PCMSK1

• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8

Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on

the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

Bit

6543210

––––––

PCIF1

PCIF0

PCIFR

Read/Write

R/W

Initial Value

Bit

543

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

PCINT9

PCINT8

PCMSK1

Read/Write

R/W

Initial Value

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