ATtiny167-ESSZ datasheet(99/282 Pages) ATMEL

99 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less

than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the

user is in doubt whether the time before re-entering Power-save mode is sufficient, the

following algorithm can be used to ensure that one TOSC1 cycle has elapsed:

Write a value to TCCR0A, TCNT0, or OCR0A.

Wait until the corresponding Update Busy flag in ASSR returns to zero.

Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always

running, except in Power-down mode. After a Power-up Reset or wake-up from

Power-down mode, the user should be aware of the fact that this oscillator might take as

long as one second to stabilize. The user is advised to wait for at least one second before

using Timer/Counter0 after power-up or wake-up from Power-down mode. The contents of

all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down

mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use

or a clock signal is applied to the XTAL1 pin.

• Description of wake up from Power-save mode when the timer is clocked asynchronously:

When the interrupt condition is met, the wake up process is started on the following cycle of

the timer clock, that is, the timer is always advanced by at least one before the processor

can read the counter value. After wake-up, the MCU is halted for four cycles, it executes

the interrupt routine, and resumes execution from the instruction following SLEEP.

• Reading of the TCNT0 Register shortly after wake-up from Power-save may give an

incorrect result. Since TCNT0 is clocked on the asynchronous clock, reading TCNT0 must

be done through a register synchronized to the internal I/O clock domain (CPU main clock).

Synchronization takes place for every rising XTAL1 edge. When waking up from

Power-save mode, and the I/O clock (clk

I/O) again becomes active, TCNT0 will read as the

previous value (before entering sleep) until the next rising XTAL1 edge. The phase of the

XTAL1 clock after waking up from Power-save mode is essentially unpredictable, as it

depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as

follows:

Write any value to either of the registers OCR0A or TCCR0A.

Wait for the corresponding Update Busy Flag to be cleared.

Read TCNT0.

• During asynchronous operation, the synchronization of the interrupt flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting

of the interrupt flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

ATtiny167-ESSZ датащи(PDF) 99 Page - ATMEL Corporation