ATtiny167-ESSZ datasheet(98/282 Pages) ATMEL

98 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

Figure 10-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 10-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (f

clk_I/O/8)

10.9

Asynchronous Operation of Timer/Counter0

When Timer/Counter0 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter0, the timer registers TCNT0, OCR0A, and TCCR0A might be corrupted. A

safe procedure for switching clock source is:

Disable the Timer/Counter0 interrupts by clearing OCIE0A and TOIE0.

Select clock source by setting AS0 and EXCLK as appropriate.

Write new values to TCNT0, OCR0A, and TCCR0A.

To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.

Clear the Timer/Counter0 interrupt flags.

Enable interrupts, if needed.

• If an 32.768 kHz watch crystal is used, the CPU main clock frequency must be more than

four times the Oscillator or external clock frequency.

• When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred

to a temporary register, and latched after two positive edges on TOSC1. The user should

not write a new value before the contents of the temporary register have been transferred

to its destination. Each of the three mentioned registers have their individual temporary

progress. To detect that a transfer to the destination register has taken place, the

Asynchronous Status Register – ASSR has been implemented.

• When entering Power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the

user must wait until the written register has been updated if Timer/Counter0 is used to

wake up the device. Otherwise, the MCU will enter sleep mode before the changes are

effective. This is particularly important if the Output Compare0 interrupt is used to wake up

the device, since the Output Compare function is disabled during writing to OCR0A or

TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the

OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and

the MCU will not wake up.

• If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must

be taken if the user wants to re-enter one of these modes: The interrupt logic needs one

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

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