ATtiny167-ESSZ datasheet(155/282 Pages) ATMEL

155 / 282 page

155

7728D–AVR–07/09

ATtiny87/ATtiny167

Referring to the timing diagram (Figure 14-5), a bus transfer involves the following steps:

The a start condition is generated by the Master by forcing the SDA low line while the

SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift

the USI Data Register bit must be set to one for the output to be enabled. The slave

device’s start detector logic (Figure 14-6.) detects the start condition and sets the

USISIF Flag. The flag can generate an interrupt if necessary.

In addition, the start detector will hold the SCL line low after the Master has forced an

negative edge on this line (B). This allows the Slave to wake up from sleep or com-

plete its other tasks before setting up the USI Data Register to receive the address.

This is done by clearing the start condition flag and reset the counter.

The Master set the first bit to be transferred and releases the SCL line (C). The Slave

samples the data and shift it into the USI Data Register at the positive edge of the

SCL clock.

After eight bits are transferred containing slave address and data direction (read or

write), the Slave counter overflows and the SCL line is forced low (D). If the slave is

not the one the Master has addressed, it releases the SCL line and waits for a new

start condition.

If the Slave is addressed it holds the SDA line low during the acknowledgment cycle

before holding the SCL line low again (i.e., the Counter Register must be set to 14

before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables

its output. If the bit is set, a master read operation is in progress (i.e., the slave drives

the SDA line) The slave can hold the SCL line low after the acknowledge (E).

Multiple bytes can now be transmitted, all in same direction, until a stop condition is

given by the Master (F). Or a new start condition is given.

If the Slave is not able to receive more data it does not acknowledge the data byte it has last

received. When the Master does a read operation it must terminate the operation by force the

acknowledge bit low after the last byte transmitted.

Figure 14-6. Start Condition Detector, Logic Diagram

14.3.5

Start Condition Detector

The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of

50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only

enabled in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the proces-

sor from the Power-down sleep mode. However, the protocol used might have restrictions on

the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time

set by the CKSEL Fuses (see “Clock Systems and their Distribution” on page 24) must also be

taken into the consideration. Refer to the USISIF bit description on page 157 for further

details.

SDA

SCL

Write( USISIF)

CLOCK

HOLD

USISIF

CLR

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