ATtiny167-ESSZ datasheet(46/282 Pages) ATMEL

46 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

5.8.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume

power. In the deeper sleep modes, this will contribute significantly to the total current con-

sumption. Refer to Section 6.3 “Watchdog Timer” on page 53 for details on how to configure

the Watchdog Timer.

5.8.7

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk

I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section Section 9.2.6 “Digital Input Enable and Sleep Modes” on page

72 for details on which pins are enabled. If the input buffer is enabled and the input signal is

left floating or have an analog signal level close to Vcc/2, the input buffer will use excessive

power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to Vcc/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to Section 17.11.6 “DIDR1 – Digital Input Disable Register 1” on page 210 and

Section 17.11.5 “DIDR0 – Digital Input Disable Register 0” on page 209 for details.

5.8.8

On-chip Debug System

If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode,

the main clock source is enabled and hence always consumes power. In the deeper sleep

modes, this will contribute significantly to the total current consumption.

5.9

5.9.1

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bits 7..3 Res: Reserved Bits

These bits are unused bits in the ATtiny87/167, and will always read as zero.

• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0

These bits select between the four available sleep modes as shown in Table 5-2.

Bit

654321

–

––––

SM1

SM0

SMCR

Read/Write

RRR

R/W

Initial Value

000000

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