ATtiny167-ESSZ datasheet(156/282 Pages) ATMEL

156 / 282 page

156

7728D–AVR–07/09

ATtiny87/ATtiny167

14.4

Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative tasks

due to its flexible design.

14.4.1

Half-duplex Asynchronous Data Transfer

By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more com-

pact and higher performance UART than by software only.

14.4.2

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will generate an increment.

14.4.3

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

14.4.4

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This fea-

ture is selected by the USICS1 bit.

14.4.5

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

14.5

14.5.1

USIDR – USI Data Register

• Bits 7:0 – USID7..0: USI Data

When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly.

If a serial clock occurs at the same cycle the register is written, the register will contain the

value written and no shift is performed. A (left) shift operation is performed depending of the

USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a

Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note

that even when no wire mode is selected (USIWM1..0 = 0) both the external data input

(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the output

latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transpar-

ent) during the first half of a serial clock cycle when an external clock source is selected

(USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The

output will be changed immediately when a new MSB written as long as the latch is open. The

latch ensures that data input is sampled and data output is changed on opposite clock edges.

Bit

USID7

USID6

USID5

USID4

USID3

USID2

USID1

USID0

USIDR

Read/Write

R/W

Initial Value

ATtiny167-ESSZ датащи(PDF) 156 Page - ATMEL Corporation

ATtiny167-ESSZ датащи(HTML) 156 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL