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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 75 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 75 Page - ATMEL Corporation |
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75 / 282 page  75 7728D–AVR–07/09 ATtiny87/ATtiny167 9.3.1 MCU Control Register – MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See “Con- figuring the Pin” on page 68 for more details about this feature. 9.3.2 Port Control Register – PORTCR • Bits 5, 4 – BBMx: Break-Before-Make Mode Enable When these bits are written to one, the port-wise Break-Before-Make mode is activated. The intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further information, see “Break-Before-Make Switching” on page 69. • Bits 1, 0 – PUDx: Port-Wise Pull-up Disable When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pu ll-ups ({DDxn, PORTxn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD) from the MCUCR register. See “Configuring the Pin” on page 68 for more details about this feature. Bit 7 6 5 4 3 2 1 0 – BODS BODSE PUD – – – – MCUCR Read/Write R R/W R/W R/W R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 - - BBMB BBMA - - PUDB PUDA PORTCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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