ATtiny167-ESSZ datasheet(154/282 Pages) ATMEL

номер детали	ATtiny167-ESSZ

подробное описание детали	8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

PDF	282 Pages

Scroll/Zoom	100%

производитель	ATMEL [ATMEL Corporation]

домашняя страница	http://www.atmel.com

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154 / 282 page

154

7728D–AVR–07/09

ATtiny87/ATtiny167

Figure 14-4. Two-wire Mode Operation, Simplified Diagram

Figure 14-4 shows two USI units operating in Two-wire mode, one as Master and one as

Slave. It is only the physical layer that is shown since the system operation is highly depen-

dent of the communication scheme used. The main differences between the Master and Slave

operation at this level, is the serial clock generation which is always done by the Master, and

only the Slave uses the clock control unit. Clock generation must be implemented in software,

but the shift operation is done automatically by both devices. Note that only clocking on nega-

tive edge for shifting data is of practical use in this mode. The slave can insert wait states at

start or end of transfer by forcing the SCL clock low. This means that the Master must always

check if the SCL line was actually released after it has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that

the transfer is completed. The clock is generated by the master by toggling the USCK pin via

the PORT Register.

The data direction is not given by the physical layer. A protocol, like the one used by the

TWI-bus, must be implemented to control the data flow.

Figure 14-5. Two-wire Mode, Typical Timing Diagram

MASTER

SLAVE

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Two-wire Clock

Control Unit

HOLD

SCL

PORTxn

SDA

SCL

VCC

ADDRESS

1 - 7

R/W

ACK

1 - 8

DATA

ACK

1 - 8

DATA

SDA

SCL

A B

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