ATtiny167-ESSZ datasheet(100/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

10.10 Timer/Counter0 Prescaler

Figure 10-12. Prescaler for Timer/Counter0

The clock source for Timer/Counter0 is named clk

T0S. clkT0S is by default connected to the

main system I/O clock clk

IO. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro-

nously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as

a Real Time Counter (RTC).

A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an indepen-

dent clock source for Timer/Counter0.

A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this

configuration.

For Timer/Counter0, the possible prescaled selections are: clk

T0S/8, clkT0S/32, clkT0S/64,

clk

T0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be

selected. Setting the PSR0 bit in GTCCR resets the prescaler. This allows the user to operate

with a predictable prescaler.

10.11 8-bit Timer/Counter Register Description

• Timer/Counter0 Control Register A – TCCR0A

• Bit 7:6 – COM0A1:0: Compare Match Output Mode A

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-

nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A

pin must be set in order to enable the output driver.

10-BIT T/C PRESCALER

TIMER/COUNTERn CLOCK SOURCE

clk

I/O

clk

TnS

ASn

CSn0

CSn1

CSn2

PSRn

Clear

clk

XTAL2

EXCLK

Oscillator

XTAL1

Bit

210

COM0A1

COM0A0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

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