ATtiny167-ESSZ datasheet(157/282 Pages) ATMEL

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157

7728D–AVR–07/09

ATtiny87/ATtiny167

Note that the corresponding Data Direction Register to the pin must be set to one for enabling

data output from the USI Data Register.

14.5.2

USIBR – USI Buffer Register

• Bits 7:0 – USID7..0: USI Buffer

The content of the Serial Register is loaded to the USI Buffer Register when the transfer is

completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data

Buffer can be accessed when the CPU reads the received data. This gives the CPU time to

handle other program tasks too as the controlling of the USI is not so timing critical. The USI

flags as set same as when reading the USIDR register.

14.5.3

USISR – USI Status Register

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is

detected. When output disable mode or Three-wire mode is selected and (USICSx = 11

b &

USICLK = 0) or (USICS = 10

b & USICLK = 0), any edge on the SCK pin sets the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the

Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the

USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is

detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag.

This signal is useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value.

The flag is only valid when Two-wire mode is used. This signal is useful when implementing

Two-wire bus master arbitration.

Bit

USIB7

USIB6

USIB5

USIB4

USIB3

USIB2

USIB1

USIB0

USIBR

Read/Write

Initial Value

Bit

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

Read/Write

R/W

Initial Value

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