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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 24 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 24 Page - ATMEL Corporation |
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24 / 282 page  24 7728D–AVR–07/09 ATtiny87/ATtiny167 4. System Clock and Clock Options The ATtiny87/167 provides a large number of clock sources. They can be divided into two cat- egories: internal and external. Some external clock sources can be shared with the asynchronous timer. After reset, the clock source is determined by the CKSEL Fuses. Once the device is running, software clock switching is possible to any other clock sources. Hardware controls are provided for clock switching management but some specific proce- dures must be observed. Clock switching should be performed with caution as some settings could result in the device having an incorrect configuration. 4.1 Clock Systems and their Distribution Figure 4-1 presents the principal clock systems in the AVR and their distribution. All of the clocks may not need to be active at any given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes or by using features of the dynamic clock switch circuit (See “Power Management and Sleep Modes” on page 42 and “Dynamic Clock Switch” on page 31). The clock systems are detailed below. Figure 4-1. Clock Distribution Modules clk I/O clk ASY AVR Clock Control Unit clk CPU clk FLASH Source Clock Watchdog Timer Watchdog Oscillator Reset Logic Prescaler Multiplexer Watchdog Clock Low-frequency Crystal Oscillator Crystal Oscillator External Clock clk ADC Asynchronous Timer/Counter0 General I/O ADC CPU Core RAM Flash and EEPROM Calibrated RC Oscillator PB5 / XTAL2 / CLKO PB4 / XTAL1 / CLKI CKOUT Fuse Clock Switch |
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