ATtiny167-ESSZ datasheet(35/282 Pages) ATMEL

35 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

In the first domain, the user (code) can easily check the validity of the clock(s) (See “COUT

Command” on page 33.).

In the second domain, the lack of a clock results in the code not running. Thus, the presence

of the system clock needs to be monitored by hardware.

Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is per-

formed only if the code reaches some specific software labels, reaching these labels proves

that the system clock is running. Otherwise the watchdog reset is enabled. This behavior can

be considered as a clock monitoring.

If the standard watchdog functionality is not desired, the ATtiny87/167 watchdog permits the

system clock to be monitored without having to resort to the complexity of a full software

watchdog handler. The solution proposed in the ATtiny87/167 is to automate the watchdog

reloading with only one command, at the beginning of the session.

So, to monitor the system clock, the user will have two options:

Using the standard watchdog features (software reload),

Or using the automatic reloading (hardware reload).

The two options are exclusive.

Note:

Warning:

These two options make sense ONLY if the clock source at RESET is an INTERNAL SOURCE.

The fuse settings determine this operation.

Figure 4-6.

Watchdog Timer with Automatic Reloading.

The ‘Enable Watchdog in Automatic Reload Mode’ command has priority over the standard

watchdog enabling. In this mode, only the reset function of the watchdog is enabled (no more

watchdog interrupt). The WDP3..0 bits of the WDTCSR register always determine the watch-

dog timer prescaling.

As the watchdog will not be active before executing the ‘Enable Watchdog in Automatic

Reload Mode’ command, it is recommended to activate this command before switching to an

external clock source (See note on page 35).

Notes:

1. ONLY the reset (watchdog reset included) disables this function. The Watchdog System

Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause.

2. ONLY clock frequencies greater than or equal to (4 * WatchDog Clock Frequency) can be

monitored.

Internal Bus

WDTCSR

Checker

Reload

Enable

System CLK

Automatic

Reloading

Mode

WatchDog Clock

Interrupt

Reset

WatchDog

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