M16CSLASH26 datasheet(223/239 Pages) RENESAS

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

217

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

SRD1 bits

SR15 (bit7)

SR14 (bit6)

SR13 (bit5)

SR12 (bit4)

SR11 (bit3)

SR10 (bit2)

SR9 (bit1)

SR8 (bit0)

Status Register 1 (SRD1)

Status register 1 indicates the status of serial communications, results from ID checks and results from

check sum comparisons. It can be read after the SRD by writing the read status register command (7016).

Also, status register 1 is cleared by writing the clear status register command (5016).

Table 1.22.4 gives the definition of each status register 1 bit. “0016” is output when power is turned ON

and the flag status is maintained even after the reset.

Table 1.22.4. Status register 1 (SRD1)

Boot Update Completed Bit (SR15)

This flag indicates whether the control program was downloaded to the RAM or not, using the down-

load function.

Flash Identification Value (SR14)

This flag indicates whether the flash memor type is HND or DINOR.

Check Sum Match Bit (SR12)

This flag indicates whether the check sum matches or not when a program, is downloaded for execu-

tion using the download function.

ID Check Completed Bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check.

Data Receive Time Out (SR9)

This flag indicates when a time out error is generated during data reception. If this flag is attached during

data reception, the received data is discarded and the microcomputer returns to the command wait state.

Status name

Boot update completed bit

Flash identification value

Reserved

Check sum match bit

ID check completed bits

Data receive time out

Reserved

Definition

"1"

"0"

Update co

mpleted

HND

Match

Not verified

Verification mismatch

Reserved

Verified

Time out

Not update

DINOR

Mismatch

Normal operation

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