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M16C/26 датащи(PDF) 180 Page - Renesas Technology Corp

номер детали M16C/26
подробное описание детали  16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
PDF  239 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M16C/26 датащи(HTML) 180 Page - Renesas Technology Corp

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Electrical Characteristics
174
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Table 1.18.6. Low Voltage Detection Circuit Electrical Characteristics (Note 1)
Symbol
Standard
Typ.
Unit
Measuring condition
Min.Max.
Parameter
Vdet4
Power supply down detection voltage (Note 1)
V
3.8
4.4
3.3
Vdet3
Reset level detection voltage (Note 1)
V
2.8
3.6
2.2
V
0.8
2.9
4.0
Vdet3s
Low voltage reset retention voltage (Note 2)
Vdet3r
Low voltage reset release voltage
2.2
V
Note 1: VDET4 > VDET3
Note 2: VDET3s is the min voltage at which "hardware reset 2" is maintained. Below this voltage, "hardware reset 1" (using reset pin) must be
applied in order to resume operation.
VCC = 0.8 to 5.5V
Table 1.18.7. Power Supply Circuit Timing Characteristics
µs
Symbol
Standard
Typ.
Unit
Measuring condition
Min.Max.
Parameter
150
150
6 (Note 1)
50
td(W-S)
20
td(M-L)
Time for internal power supply stabilization when main clock oscillation starts
20
td(S-R)
Hardware reset 2 release wait time
µs
td(E-A)
Low voltage detection circuit operation start time (Note 3)
µs
µs
ms
td(R-S)
S
release time (Note 2)
TOP
Low power dissipation mode wait mode release time (Note 2)
Note 1: When Vcc = 5V
Note 2: This is the time between interrupt for (STOP/WAIT) mode release and resumption of CPU clock operation.
Note 3: After enabling low voltage detection, this time is required before proper detection can occur.
VCC = 2.7 to 5.5V
VCC = VDET3r to 5.5V
VCC = 2.7 to 5.5V
Table 1.18.8. Hardware Reset 2 Release Wait Time
CPU clock
td(S-R)
Vdet3r
VCC
Table 1.18.9. STOP Release Time
Interrupt for
stop mode
release
CPU clock
td(R-S)



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