M16CSLASH26 datasheet(159/239 Pages) RENESAS

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A-D Converter

153

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P100 to P107 also function as the analog signal input pins AN0 to AN7. The direction registers of these pins

for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the

resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used.

Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the

A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF.

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits

are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are

stored in the even addresses. Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the

block diagram of the A-D converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AVCC (VCC)

Operating clock fAD (Note 2)

fAD, fAD/2, fAD/3, fAD/4, fAD/6, or fAD/12 where fAD=f(XIN)

Resolution

8-bit or 10-bit (selectable)

Integral nonlinearity error

When AVCC = VREF = 5V

• With 8-bit resolution: ±2LSB

• With 10-bit resolution: ±3LSB

When AVCC = VREF = 3.3V

• With 8-bit resolution: ±2LSB

• With 10-bit resolution: ±5LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

8pins (AN0 to AN7)

A-D conversion start condition • Software trigger

A-D conversion starts when the A-D conversion start flag changes to “1”

• External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is “1” and the

ADTRG/P15 input (shared with INT3) changes from “H” to “L”

Conversion speed per pin • Without sample and hold function

8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles

• With sample and hold function

8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles

Table 1.16.1. Performance of A-D converter

Note 1: Does not depend on use of sample and hold function.

Note 2: Divide the fAD if f(XIN) exceeds 10MHZ, and make

fAD frequency equal to or less than 10MHz.

Without sample and hold function, set the

fAD frequency to 250kHZ min.

With the sample and hold function, set the

fAD frequency to 1MHZ min.

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