M16CSLASH26 datasheet(122/239 Pages) RENESAS

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Renesas Technology Corp.

Serial I/O

116

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Figure 1.15.8. Serial I/O-related registers (5)

Note: When using multiple pins to output the transfer clock, the following requirements must be met:

* UART1 internal/external clock select bit (bit 3 at address 03A816) = 0 .

UART transmit/receive control register 2

Symbol

Address

When reset

UCON

03B016

X00000002

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

CLKMD0

CLKMD1

UART0 transmit

interrupt cause select bit

UART0 continuous

receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enable

UART1 continuous

receive mode enable bit

CLK/CLKS select bit 0

UART1 transmit

interrupt cause select bit

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Normal mode

(CLK output is CLK1 only)

1 : Transfer clock output

from multiple pins

function selected

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Nothing is assigned.

In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

Must always be 0

U0IRS

U1IRS

U0RRM

U1RRM

Invalid

CLK/CLKS select

bit 1 (Note)

Valid when bit 5 = 1

0 : Clock output to CLK1

1 : Clock output to CLKS1

UART2 special mode register

Symbol

Address

When reset

U2SMR

037716

X00000002

b7 b6

b1 b0

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

ABSCS

ACSE

SSS

I2C mode select bit

Bus busy flag

0 : STOP condition detected

1 : START condition detected

Bus collision detect

sampling

clock select bit

Arbitration lost detecting

flag control bit

0 : Normal mode

1 : I2C mode

0 : Update per bit

1 : Update per byte

IICM

ABC

BBS

0 : Ordinary

1 : Falling edge of RXDi

Transmit start condition

select bit

Must always be 0

0 : Rising edge of transfer

clock

1 : Underflow signal of timer Aj

(Note 2)

Auto clear function

select bit of transmit

enable bit

0 : No auto clear function

1 : Auto clear at occurrence of

bus collision

Must always be 0

Note 1: Nothing but 0 may be written.

Note 2: Underflow signal of timer A0 in UART2.

(Note1)

Must always be 0

RCSP

Separate CTS/RTS bit

0 : CTS/RTS shared pin

1 : CTS/ RTS separated

0 : CTS/RTS shared pin

1 : CTS/ RTS separated

Nothing is assigned.

In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.

(b3)

Reserved bit

Must always be 0.

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