LFSC datasheet(31/237 Pages) LATTICE

31 / 237 page

2-27

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Table 2-9. Supported Input Standards

Input Standard

VREF (Nom.)

VCCIO

1 (Nom.)

On-chip Termination

Single Ended Interfaces

LVTTL33

—

3.3

None

LVCMOS 33, 25, 18, 15, 12

—

3.3/2.5/1.8/1.5/1.2 None

PCI33, PCIX33, AGP1X33

—

3.3

None

PCIX15

0.75

1.5

None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

AGP2X33

1.32

—

None

HSTL18_I, II

0.9

1.8

None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

HSTL18_III, IV

1.08

1.8

None / VCCIO: 50

HSTL15_I, II

0.75

1.5

None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

HSTL15_III, IV

0.9

1.5

None / VCCIO: 50

SSTL33_I, II

1.5

3.3

None

SSTL25_I, II

1.25

2.5

None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

SSTL18_I, II

0.9

1.8

None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

GTL+, GTL

1.0 / 0.8

1.5 / 1.2

None / VCCIO: 50

Differential Interfaces

SSTL18D_I, II

—

1.8

None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,

220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

SSTL25D_I, II

—

2.5

None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,

220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

SSTL33D_I, II

—

3.3

None

HSTL15D_I, II

—

1.5

None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,

220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

HSTL18D_I, II

—

1.8

None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,

220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210

LVDS

—

None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,

220, 240

Mini-LVDS

—

None / Diff: 120, 150 / Diff to VCMT: 120, 150

BLVDS25

—

None

MLVDS25

—

None

HYPT (Hyper Transport)

—

None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,

220, 240

RSDS

—

None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,

220, 240

LVPECL33

—

≤2.5

None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,

220, 240

1. When not speciﬁed VCCIO can be set anywhere in the valid operating range.

2. VCCIO needed for on-chip termination to VCCIO/2 or VCCIO only. VCCIO is not speciﬁed for off-chip termination or VTT termination.

3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.

LFSC датащи(PDF) 31 Page - Lattice Semiconductor

LFSC датащи(HTML) 31 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL