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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LFSC датащи(PDF) 61 Page - Lattice Semiconductor |
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LFSC датащи(HTML) 61 Page - Lattice Semiconductor |
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61 / 237 page  3-17 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet LatticeSC/M Internal Timing Parameters 1 Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5% Parameter Symbol Description -7 -6 -5 Units Min. Max. Min. Max. Min. Max. PFU Logic Mode Timing tLUT4_PFU CTOF_DEL LUT4 delay (A to D inputs to F output) — 0.045 — 0.050 — 0.054 ns tLUT5_PFU MTOOFX_DEL LUT5 delay (inputs to output) — 0.152 — 0.172 — 0.192 ns tLSR_PFU LSR_DEL Set/Reset to output (asynchronous) — 0.378 — 0.426 — 0.474 ns tSUM_PFU M_SET Clock to Mux (M0,M1) input setup time 0.113 — 0.131 — 0.148 — ns tHM_PFU M_HLD Clock to Mux (M0,M1) input hold time -0.041 — -0.046 — -0.052 — ns tSUD_PFU DIN_SET Clock to D input setup time 0.072 — 0.083 — 0.094 — ns tHD_PFU DIN_HLD Clock to D input hold time -0.028 — -0.032 — -0.035 — ns tCK2Q_PFU REG_DEL Clock to Q delay, D-type register configuration — 0.224 — 0.252 — 0.279 ns tLE2Q_PFU LTCH_DEL Clock to Q delay latch configuration — 0.294 — 0.331 — 0.367 ns tLD2Q_PFU TLTCH_DEL D to Q throughput delay when latch is enabled — 0.300 — 0.338 — 0.376 ns PFU Memory Mode Timing tCORAM_PFU CLKTOF_DEL Clock to Output — 0.575 — 0.649 — 0.724 ns tSUDATA_PFU DIN_SET Data Setup Time -0.024 — -0.026 — -0.027 — ns tHDATA_PFU DIN_HLD Data Hold Time 0.075 — 0.084 — 0.094 — ns tSUADDR_PFU WAD_SET Address Setup Time -0.176 — -0.196 — -0.215 — ns tHADDR_PFU WAD_HLD Address Hold Time 0.110 — 0.124 — 0.138 — ns tSUWREN_PFU WE_SET Write/Read Enable Setup Time 0.014 — 0.019 — 0.024 — ns tHWREN_PFU WE_HLD Write/Read Enable Hold Time 0.078 — 0.086 — 0.094 — ns PIC Timing PIO Input/Output Buffer Timing tIN_PIO IN_DEL Input Buffer Delay(LVCMOS25) — 0.578 — 0.661 — 0.744 ns tOUT_PIO DOPADI_DEL Output Buffer Delay(LVCMOS25) — 2.712 — 3.027 — 3.395 ns tSUI_PIO DIN_SET Input Register Setup Time (Data Before Clock) -0.156 — -0.175 — -0.194 — ns tHI_PIO DIN_HLD Input Register Hold Time (Data after Clock) -0.267 — -0.306 — -0.345 — ns tCOO_PIO CK_DEL Output Register Clock to Output Delay — 0.513 — 0.571 — 0.639 ns tSUCE_PIO CE_SET Input Register Clock Enable Setup Time — 0.000 — 0.000 — 0.000 ns tHCE_PIO CE_HLD Input Register Clock Enable Hold Time — 0.129 — 0.145 — 0.161 ns tSULSR_PIO LSR_SET Set/Reset Setup Time 0.057 — 0.060 — 0.063 — ns tHLSR_PIO LSR_HLD Set/Reset Hold Time -0.151 — -0.159 — -0.169 — ns tLE2Q_PIO CK_DEL Input Register Clock to Q delay latch configuration — 0.335 — 0.372 — 0.410 ns tLD2Q_PIO DIN_DEL Input Register D to Q throughput delay when latch is enabled — 0.578 — 0.647 — 0.717 ns |
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