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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LFSC датащи(PDF) 11 Page - Lattice Semiconductor |
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LFSC датащи(HTML) 11 Page - Lattice Semiconductor |
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11 / 237 page  2-7 Architecture Lattice Semiconductor LatticeSC/M Family Data Sheet • Two outputs per PLL • Clock divider outputs • Digital Clock Select (DCS) block outputs • Three outputs per SERDES quad Figure 2-5 shows the arrangement of the primary clock sources. Figure 2-5. Clock Sources Primary Clock Routing The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6 shows this clock routing. SERDES PLL DCS DCS DCS DCS DCS DCS DLL DLL DLL DLL DLL DLL DCS Primary/ Edge Clock PIOs DCS PLL PLL (3 per SERDES Channel) (3 per SERDES Channel) 4 8 24 24 Primary Clock Sources PLL PLL DLL DLL DLL DLL PLL DLL DLL PLL PLL SERDES Primary/ Edge Clock PIOs Edge Clock PIOs Clock Dividers Clock Dividers Clock Dividers Clock Dividers Clock Dividers Primary/ Edge Clock PIOs Primary/ Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs |
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