LFSC datasheet(35/237 Pages) LATTICE

35 / 237 page

2-31

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs:

• Parallel to VCCIO or GND

• Parallel to VCCIO/2

• Parallel to VTT

Figure 2-28 shows the single ended input schemes that are supported. The nominal values of the termination resis-

tors are shown in Table 2-9.

Figure 2-28. Input Termination Schemes

In many situations designers can chose whether to use Thevenin or parallel to VTT termination. The Thevenin

approach has the beneﬁt of not requiring a termination voltage to be applied to the device. The parallel to VTT

approach consumes less power.

VTT Termination Resources

Each I/O bank, except bank 1, has a number of VTT pins that must be connected if VTT is used. Note VTT pins can

sink or source current and the power supply they are connected to must be able to handle the relatively high currents

associated with the termination circuits. Note: VTT is not available in all package styles.

On-chip parallel termination to VTT is supported at the receiving end only. On-chip parallel output termination to VTT is

not supported.

The VTT internal bus is also connected to the internal VCMT node. Thus in one bank designers can implement either

VTT termination or VCMT termination for differential inputs.

DDRII/RLDRAMII Termination Support

The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to VTT

be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required cir-

cuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet.

Termination Type

Discrete Off-Chip Solution

Lattice On-Chip Solution

Parallel termination to

VCCIO/2 receiving end

Parallel termination to

to VCCIO, or parallel to

GND receiving end

VCCIO or GND

ON-chip

OFF-chip

VCCIO2

ON-chip

OFF-chip

VTT

ON-chip

OFF-chip

ON-chip

OFF-chip

VTT

VCCIO or GND

ON-chip

OFF-chip

VCCIO

GND

ON-chip

OFF-chip

2Zo

Parallel termination to

VTT at receiving end

LFSC датащи(PDF) 35 Page - Lattice Semiconductor

LFSC датащи(HTML) 35 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL