LFSC datasheet(52/237 Pages) LATTICE

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3-8

DC and Switching Characteristics

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

MLVDS

The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled imped-

ance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs.

MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The

scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals.

Figure 3-1. MLVDS Multi-Point Output Example

Table 3-1. MLVDS DC Conditions

Over Recommended Operating Conditions

Nominal

Symbol

Description

Zo = 50

Zo = 70

Units

ZOUT

Output impedance

ohm

RTLEFT

Left end termination

ohm

RTRIGHT

Right end termination

ohm

VOH

Output high voltage

1.50

1.575

VOL

Output low voltage

1.00

0.925

VOD

Output differential voltage

0.50

0.65

VCM

Output common mode voltage

1.25

IDC

DC output current

20.0

18.5

1. For input buffer, see LVDS table.

Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential

2.5V

. . .

50-70 ohms, +/- 1%

. . .

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