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LFSC датащи(PDF) 25 Page - Lattice Semiconductor

номер детали LFSC
подробное описание детали  LatticeSC/M Family Data Sheet
PDF  237 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFSC датащи(HTML) 25 Page - Lattice Semiconductor

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2-21
Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
Figure 2-22. Output Register Block
1
Figure 2-23. Output/Tristate DDR/Shift Register Block
DDR/Shift Register Block
•
DDR
• DDR + half clock
• DDR + shift x2
• DDR + shift x42
• Shift x2
• Shift x42
Notes:
1. CE, Update, Set and Reset not shown for clarity.
2. By four shift modes utilizes DDR/Shift register block from paired PIO.
3. DDR/Shift register block shared with tristate block.
HCLKOUT
LCLKOUT
OPOS0
From
Routing
To
Tri-state
Block
DO
(to PURESPEED
I/O Buffer)
From
Control
MUX
ONEG0
OPOS1
ONEG1
SDR
Register
Bypass Used for
DDR/DDRX Modes
Shift x2 / x4
Output
HCLKOUT
LCLKOUT
From paired PIO
( x4 shift modes)
To paired PIO
(x4 shift modes)
POS Update
OPOS0
(Can act as OPOS2
when paired)
NEG Update
OPOS1
(Can act as OPOS3
when paired)
Bypass Used for
DDR/DDRX Modes
From paired PIO
( x4 shift modes)
To paired PIO
(x4 shift modes)
ONEG0
(Can act as ONEG2
when paired)
ONEG1
(Can act as ONEG3
when paired)
TSDDR/DDRX
ODDR/DDR/
X2/X4



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