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LFSC датащи(PDF) 70 Page - Lattice Semiconductor

номер детали LFSC
подробное описание детали  LatticeSC/M Family Data Sheet
PDF  237 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFSC датащи(HTML) 70 Page - Lattice Semiconductor

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3-26
DC and Switching Characteristics
Lattice Semiconductor
LatticeSC/M Family Data Sheet
sysCLOCK DLL Timing
Over Recommended Operating Conditions
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
100
700
MHz
fOUTOP
Output Clock Frequency (CLKOP)
100
700
MHz
fOUTOS
Output Clock Frequency (CLKOS)
25
700
MHz
AC Characteristics
tDUTY
Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, 50% duty cycle input clock,
duty cycle correction turned off,
time reference delay mode)
38—62
%
tDUTYRD
Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, time reference delay mode)
45—55
%
tDUTYCIR
Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, clock injection removal mode)
40—60
%
tOPJIT
1
Output Clock Period Jitter
200
ps
tCPJIT
1
Output Clock Cycle-to-Cycle Jitter
200
ps
tSKEW
Output Clock to Clock Skew (Between
Two Outputs with the Same Phase
Setting)
100
ps
tLOCK
DLL Lock-in Time
8
18500
cycles
tIDUTY
Input Clock Duty Cycle
Applies to all operating conditions
35
65
%
tIPJIT
Input Clock Period Jitter
+/- 250
ps
tHI
Input Clock High Time
At 80% level
500
ps
tLO
Input Clock Low Time
At 20% level
500
ps
tRSWD
Reset Signal Pulse Width
3
ns
tFDEL
Timeshift Delay Step Size
35
45
80
ps
tDLL
Delay Through the DLL when No Delay
Taps are Chosen but Not in Bypass
Mode.
760
ps
1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps.



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