LFSC datasheet(79/237 Pages) LATTICE

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Pinout Information

Lattice Semiconductor

LatticeSC/M Family Data Sheet

MPI_STRBN

Driven active low indicates the start of a transaction on the PowerPC

bus. MPI will strobe the address bus at next rising edge of clock.

MPI_ADDR[31:14]

Address bus driven by a PowerPC bus master. Only 18-bit width is

needed. It has to be the least signiﬁcant bit of the PowerPC 32-bit

address A[31:14].

MPI_DAT[n:0]

I/O

Selectable data bus width from 8, and 16-bit. Driven by a bus master

in a write transaction. Driven by MPI in a read transaction.

MPI_PAR[m:0]

I/O

Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for

MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for

MPI_D[23:16].

MPI_TA

Transfer acknowledge. Driven active low indicates that MPI received

the data on the write cycle or returned data on the read cycle.

MPI_TEA

Transfer Error Acknowledge. Driven active low indicates that MPI

detects a bus error on the internal system bus for current transaction.

MPI_RETRY

Active low MPI Retry requests the MPC860 to relinquish the bus and

retry the cycle.

Multi-chip Alignment (User I/O if not used.)

MCA_DONE_OUT

Multi-chip alignment done output (to second MCA chip)

MCA_DONE_IN

Multi-chip alignment done input (from second MCA chip)

MCA_CLK_P[1:2]_OUT

Multi-chip alignment clock [1:2] output (sourced by MCA master chip)

MCA_CLK_P[1:2]_IN

Multi-chip alignment clock [1:2] input (from MCA master chip

TEMP

—

Temperature sensing diode pin. Dedicated pin. Accuracy is typically

+/- 10°C.

Miscellaneous Dedicated Pins

XRES

—

External reference resistor between this pin and ground. The refer-

ence resistor is used to calibrate the programmable terminating resis-

tors used in the I/Os. Dedicated pin. Value: 1K ± 1% ohm.

DIFFRx

—

Only used if a differential driver is used in a bank. This DIFFRx must

be connected to ground via an external 1K ±1% ohm resistor for all

banks that have a differential driver.

SERDES Block (Dedicated Pins)

[A:D]_HDINPx_[L/R]

High-speed input (positive) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

[A:D]_HDINNx_[L/R]

High-speed input (negative) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

[A:D]_HDOUTPx_[L/R]

High-speed output (positive) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

[A:D]_HDOUTNx_[L/R]

High-speed output (negative) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

[A:D]_REFCLKP_[L/R]

Ref clock input (positive), aux channel on left [L] or right [R] side of

device.

[A:D]_REFCLKN_[L/R]

Ref clock input (negative), aux channel on left [L] or right [R] side of

device.

Signal Descriptions (Cont.)

Signal Name

I/O

Description

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