LFSC datasheet(27/237 Pages) LATTICE

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2-23

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Table 2-6. Input/Output/Tristate Gearing Resource Rules

Control Logic Block

The control logic block allows the modiﬁcation of control signals selected by the routing before they are used in the

PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be

enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided

to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in

the clock nets to enable Lattice’s unique cycle boosting capability.

Update Block

The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register

blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high

speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal

UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock. The values of each

from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic

Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically conﬁgure

and connect the update block when one of the DDR or shift register primitives is used.

Figure 2-25. Update Block

PURESPEED I/O Buffer

Each I/O is associated with a ﬂexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged

around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users

to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL,

LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further

enhances the utility of these buffers.

PIO

Input/Output Logic

Tri-State/Bidi

x2/x4

✓✓✓✓

N/A

✓

No I/O Logic No I/O Logic

✓

N/A

✓✓

No I/O Logic

✓

N/A

✓

No I/O Logic No I/O Logic

✓

N/A

Note: Pin can still be used without I/O logic.

POS Update

NEG Update

HCLKUP

ESLRUP

LSRUP

LCLKUP

UPDATE

÷1/2/4

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