LFSC datasheet(48/237 Pages) LATTICE

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3-4

DC and Switching Characteristics

Lattice Semiconductor

LatticeSC/M Family Data Sheet

PURESPEED I/O Recommended Operating Conditions

VCCIO (V)

VREF (V)

Standard

Min.

Typ.

Max.

Min.

Typ.

Max.

LVCMOS 33

3.135

3.3

3.465

—

LVCMOS 25

2.375

2.5

2.625

—

LVCMOS 18

1.71

1.8

1.89

—

LVCMOS 15

1.425

1.5

1.575

—

LVCMOS 12

1.14

1.2

1.26

—

LVTTL

3.135

3.3

3.465

—

PCI33

3.135

3.3

3.465

—

PCIX33

3.135

3.3

3.465

—

PCIX15

1.425

1.5

1.575

0.49VCCIO

0.5VCCIO

0.51VCCIO

AGP1X33

3.135

3.3

3.465

—

AGP2X33

3.135

3.3

3.465

0.39VCCIO

0.4VCCIO

0.41VCCIO

SSTL18_I, II

1.71

1.8

1.89

0.833

0.9

0.969

SSTL25_I, II

2.375

2.5

2.625

1.15

1.25

1.35

SSTL33_I, II

3.135

3.3

3.465

1.3

1.5

1.7

HSTL15_I, II

1.425

1.5

1.575

0.68

0.75

0.9

HSTL15_III

1, 3 and IV1, 3

1.425

1.5

1.575

0.68

0.9

HSTL 18_I

3, II3

1.71

1.8

1.89

0.816

0.9

1.08

HSTL 18_ III

1, 3, IV1, 3

1.71

1.8

1.89

0.816

1.08

GTL12

1, 3, GTLPLUS151, 3

—

0.882

1.0

1.122

LVDS

——————

Mini-LVDS

——————

RSDS

——————

HYPT (Hyper Transport)

——————

LVPECL33 (outputs)

3.135

3.3

3.465

—

LVPECL33 (inputs)

2, 4

—

≤ 2.5

————

BLVDS25

2, 3

2.375

2.5

2.625

—

MLVDS25

2, 3

2.375

2.5

2.625

—

SSTL18D_I

3, II3

1.71

1.8

1.89

—

SSTL25D_I

3, II3

2.375

2.5

2.625

—

SSTL33D_I

3, II3

3.135

3.3

3.465

—

HSTL15D_I

3, II3

1.425

1.5

1.575

—

HSTL18D_I

3, II3

1.71

1.8

1.89

—

1. Input only.

2. Inputs on chip. Outputs are implemented with the addition of external resisters.

3. Input for this standard does not depend on the value of VCCIO.

4. Inputs for this standard cannot be in 3.3V VCCIO banks (≤ 2.5V only).

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