LFSC datasheet(77/237 Pages) LATTICE

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4-3

Pinout Information

Lattice Semiconductor

LatticeSC/M Family Data Sheet

RESETN

Reset. (Also sent to general routing). During conﬁguration it resets the

conﬁguration state machine. After conﬁguration this pin can perform

the global set/reset (GSR) functions or can be used as a general input

pin.

CFGIRQN

MPI Interrupt request active low signal is controlled by system bus

interrupt controller and may be sourced from any bus error or MPI con-

ﬁguration error. It can be connected to one of MPC860 IRQ pins.

TSALLN

Tristates all I/O.

Conﬁguration Pads (User I/O if not used. Used during sysCONFIG.)

HDC/SI

High During Conﬁguration is output high until conﬁguration is com-

plete. It is used as a control output, indicating that conﬁguration is not

complete.

For SPI modes, this pin is used to download the read command and

initial read address into the Flash memory device on the falling edge

of SCK. This pin will be connected to SI of the memory. If the SPI

mode is used, the 8-bit instruction code 0x03 will be downloaded fol-

lowed by a 24-bit starting address of 0x000000 or a non-zero stat

address for partial reconﬁguration. If the SPIX mode has been

selected, the 8-bit instruction captured on D[7:0] at power-up will be

shifted in and followed by a 32-bit starting address of 0x000000.

LDCN/SCS

Low During Conﬁguration is output low until conﬁguration is complete.

It is used as a control output, indicating that conﬁguration is not com-

plete.

For SPI modes, this is an active low chip select for Flash memories. It

will go active after INITN goes high but before SCK begins. During

power up LDCN will be low. Once INITN goes high, LDCN will go high

for 100ns-200ns after which time it will go back low and conﬁguration

can begin. During the 100ns-200ns period, the read instruction will be

latched for SPIX mode.

DOUT

Serial data output that can drive the D0/DIN of daisy-chained slave

devices. The data-stream from this output will propagate preamble bits

of the bitstream to daisy-chained devices. Data out on DOUT changes

on the rising edge of CCLK.

QOUT/CEON

During daisy-chaining conﬁguration, QOUT is the serial data output

that can drive the D0/DIN of daisy-chained slave devices that do not

propagate preamble bits. Data out on QOUT changes on the rising

edge of CCLK.

During parallel-chaining conﬁguration, active low CEON enables the

cascaded slave device to receive bitstream data.

RDN

Used in the asynchronous peripheral conﬁguration mode. A low on

RDN changes D[7:3] into status outputs. WRN and RDN should not be

used simultaneously. If they are, the write strobe overrides.

WRN

When the FPGA is selected, a low on the write strobe, WRN, loads the

data on D[7:0] inputs into an internal data buffer.

CS0N CS1

Used in the asynchronous peripheral, slave parallel and MPI modes.

The FPGA is selected when CS0N is low and CS1 is high. During con-

ﬁguration, a pull-up is enabled on both except with MPI DMA access

control.

A[21:0]

I/O

In master parallel mode, A[21:0] is an output and will address the con-

ﬁguration EPROMs up to 4 MB space. For MPI conﬁguration mode,

A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be

the transfer size and A[21:20] will be the burst mode and burst in pro-

cess.

Signal Descriptions (Cont.)

Signal Name

I/O

Description

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