LFSC datasheet(24/237 Pages) LATTICE

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2-20

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Figure 2-21. Input DDR/Shift Register Block

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR

and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode),

the SDR register or the DDR/shift register block. Figure 2-22 shows the diagram of the Output Register Block.

Output SDR Register/Latch Block

The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the

clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for

set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over

CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated

from the PIO control MUX. The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the

global set-reset to be disabled on a PIO basis.

Output DDR/Shift Block

The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the

high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing

low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR

and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-22

shows a simpliﬁed block diagram of the shift register block.

Data Input

(From Delay Block)

HCLKIN

LCLKIN

POS Update

IPOS0

(Can act as IPOS2

when paired)

IPOS1

(Can act as IPOS3

when paired)

INEG0

(Can act as INEG2

when paired)

INEG1

(Can act as INEG3

when paired)

NEG Update

Used for DDR with

Half Clock Transfer

To paired PIO

for wide muxing

To paired PIO

for wide muxing

Bypass used for DDR

From paired PIO

for wide muxing

From paired PIO

for wide muxing

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