LFSC datasheet(76/237 Pages) LATTICE

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Pinout Information

Lattice Semiconductor

LatticeSC/M Family Data Sheet

PROBE_GND

—

GND signal - Connected to internal VSS node. Can be used for feed-

back to control an external board power converter. Can be uncon-

nected if not used.

PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.)

[LOC]_PLL[T, C]_FB_[A/B]

PLL feedback input. Pull-ups are enabled on input pins during conﬁgu-

ration. [LOC] indicates the corner the PLL is located in: ULC (upper

left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C]

indicates whether input is true or complement. [A, B] indicates PLL ref-

erence within the corner.

[LOC]_DLL[T, C]_FB_[C, D, E, F]

DLL feedback input. Pull-ups are enabled on input pins during conﬁgu-

ration. [LOC] indicates the corner the DLL is located in: ULC (upper

left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C]

indicates whether input is true or complement. [C, D, E, F] indicates

DLL reference within a corner. Note: E and F are only available on the

lower corners.

[LOC]_PLL[T, C]_IN[A/B]

PLL reference clock input. Pull-ups are enabled on input pins during

conﬁguration. [LOC] indicates the corner the PLL is located in: ULC

(upper left corner), URC (upper right corner), LLC (lower left corner)

and LRC (lower right corner). [T, C] indicates whether input is true or

complement.[A, B] indicates PLL reference within the corner.

[LOC]_DLL[T, C]_IN[C, D, E, F]

DLL reference clock inputs. Pull-ups are enabled on input pins during

conﬁguration. [LOC] indicates the corner the DLL is located in: ULC

(upper left corner), URC (upper right corner), LLC (lower left corner)

and LRC (lower right corner). [T/C] indicates whether input is true or

complement. [C, D, E, F] indicates DLL reference within a corner.

Note: E and F are only available on the lower corners. PCKLxy_[0:3]

can drive primary clocks, edge clocks, and CLKDIVs. PCLKxy_[4:7]

can only drive edge clocks.

PCLKxy_z

General clock inputs. x indicates whether T (true) or C (complement).

y indicates the I/O bank the clock is associated with. z indicates the

clock number within a bank.

Test and Programming (Dedicated pins. Pull-up is enabled on input pins during conﬁguration.)

TMS

Test Mode Select input, used to control the 1149.1 state machine.

TCK

Test Clock input pin, used to clock the 1149.1 state machine.

TDI

Test Data in pin, used to load data into device using 1149.1 state

machine. After power-up, this TAP port can be activated for conﬁgura-

tion by sending appropriate command. (Note: once a conﬁguration

port is selected it is locked. Another conﬁguration port cannot be

selected until the power-up sequence).

TDO

Output pin -Test Data out pin used to shift data out of device using

1149.1.

Conﬁguration Pads (Dedicated pins. Used during sysCONFIG.)

M[3:0]

Mode pins used to specify conﬁguration modes values latched on ris-

ing edge of INITN.

INITN

I/O

Open Drain pin - Indicates the FPGA is ready to be conﬁgured. During

conﬁguration, a pull-up is enabled that will pull the I/O above 1.5V.

PROGRAMN

Initiates conﬁguration sequence when asserted low. This pin always

has an active pull-up.

DONE

I/O

Open Drain pin - Indicates that the conﬁguration sequence is com-

plete, and the startup sequence is in progress.

CCLK

I/O

Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

Signal Descriptions (Cont.)

Signal Name

I/O

Description

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