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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LFSC датащи(PDF) 69 Page - Lattice Semiconductor |
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LFSC датащи(HTML) 69 Page - Lattice Semiconductor |
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69 / 237 page  3-25 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ Max. Units fIN Input Clock Frequency (CLKI, CLKFB) 2 — 1000 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) 1.5625 — 1000 MHz fVCO PLL VCO Frequency 100 — 1000 MHz fPFD Phase Detector Input Frequency 2 — 700 MHz AC Characteristics tDT Output Clock Duty Cycle Default duty cycle selected (at 50% levels) 45 — 55 % tOPJIT 1 Output Clock Period Jitter 2 MHz ≤ fPFD ≤ 10 MHz — — 200 ps fPFD > 10 MHz — — 100 ps tCPJIT 1 Output Clock Cycle-to-Cycle Jitter — — 100 ps tSKEW Output Clock-to-Clock Skew (Between Two Outputs with the Same Phase Set- ting) — — 20 ps tLOCK PLL Lock-in Time — — 1 ms tIPJIT Input Clock Period Jitter — — ±250 ps tHI Input Clock High Time At 80% level 350 — — ps tLO Input Clock Low Time At 20% level 350 — — ps tRSWA Analog Reset Signal Pulse Width 100 — — ns tRSWD Digital Reset Signal Pulse Width 3 — — ns tDEL Timeshift Delay Step Size 40 80 120 ps tRANGE Timeshift Delay Range — +/- 560 — ps fSS Spread Spectrum Modulation Frequency 30 — 500 KHz % Spread Percentage Downspread for SS Mode 0.5 — 1.5 % VCO Clock Phase Adjustment Accuracy -5 — 5 ° 1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps |
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