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LFSC датащи(PDF) 45 Page - Lattice Semiconductor |
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LFSC датащи(HTML) 45 Page - Lattice Semiconductor |
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45 / 237 page ![]() June 2008 Data Sheet DS1004 © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1004 DC and Switching_01.9 Absolute Maximum Ratings Supply Voltage VCC, VCC12, VDDIB, VDDOB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.6V Supply Voltage VCCAUX, VDDAX25, VTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 1, 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 2, 3, 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Input or I/O Tristate Voltage Applied (Banks 1, 4, 5) . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Input or I/O Tristate Voltage Applied (Banks 2, 3, 6, 7) . . . . . . . . . . . . . . . . -0.5 to 2.75V Storage Temperature (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature Under Bias (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Notes: 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot and overshoot of -2V to (VIHMAX +2) volts is permitted for a duration of <20ns. Recommended Operating Conditions Symbol Parameter Min. Max. Units VCC 5 Core Supply Voltage (Nominal 1.2V Operation) 0.95 1.26 V VCCAUX 6 Programmable I/O Auxiliary Supply Voltage 2.375 2.625 V VCCIO 1, 2, 5, 6 Programmable I/O Driver Supply Voltage (Banks 1, 4, 5) 1.14 3.45 V VCCIO 1, 2, 5, 6 Programmable I/O Driver Supply Voltage (Banks 2, 3, 6, 7) 1.14 2.625 V VCC12 4, 5 Internal 1.2V Power Supply Voltage for Configuration Logic and FPGA PLL, SERDES PLL Power Supply Voltage and SERDES Analog Supply Voltage 1.14 1.26 V VDDIB SERDES Input Buffer Supply Voltage 1.14 1.575 V VDDOB SERDES Output Buffer Supply Voltage 1.14 1.575 V VDDAX25 SERDES Termination Auxiliary Supply Voltage 2.375 2.625 V VCCJ 1, 5 Supply Voltage for IEEE 1149.1 Test Access Port 1.71 3.45 V VTT 2, 3 Programmable I/O Termination Power Supply 0.5 VCCAUX - 0.5 V tJCOM Junction Temperature, Commercial Operation 0 +85 C tJIND Junction Temperature, Industrial Operation -40 105 C 1. If VCCIO or VCCJ is set to 2.5V, they must be connected to the same power supply as VCCAUX. 2. See recommended voltages by I/O standard in subsequent table. 3. When VTT termination is not required, or used to provide the common mode termination voltage (VCMT), these pins can be left unconnected on the device. 4. VCC12 cannot be lower than VCC at any time. For 1.2V operation, it is recommended that the VCC and VCC12 supplies be tied together with proper noise decoupling between the digital VCC and analog VCC12 supplies. 5. VCC, VCCIO (all banks), VCC12 and VCCJ must reach their minimum values before configuration will proceed. 6. If VCCIO for a bank is nominally 1.2V/1.5V/1.8V, then VCCAUX must always be higher than VCCIO during power up. LatticeSC/M Family Data Sheet DC and Switching Characteristics |
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