LFSC datasheet(42/237 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Figure 2-32. PowerPCI and MPI Schematic

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LatticeSC family of devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access

port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can

operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the

data sheet.

Device Conﬁguration

All LatticeSC devices contain three possible ports that can be used for device conﬁguration. The serial port, which

supports bit-wide conﬁguration, and the sysCONFIG port that supports both byte-wide and serial conﬁguration.

The MPI port supports 8-bit, 16-bit or 32-bit conﬁguration.

The serial port supports both the IEEE Std. 1149.1 Boundary Scan speciﬁcation and the IEEE Std. 1532 In-System

Conﬁguration speciﬁcation. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins

and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for gen-

eral purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1.

On power-up, the FPGA SRAM is ready to be conﬁgured with the sysCONFIG port active. The IEEE 1149.1 serial

mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a

conﬁguration port is selected, that port is locked and another conﬁguration port cannot be activated until the next

re-initialization sequence. For additional detail refer to technical information at the end of the data sheet.

Bus

Controller

LatticeSC FPGA

To Daisy-

Chained

Devices

PowerPC

DOUT

DONE

HDC

INIT

LDC

CCLK

MPI_RTRY

RETRY

MPI_ACK

MPI_BDIP

BDIP

MPI_IRQ

IRQx

MPI_STRB

CS0

MPI_TSZ[0:1]

TSZ[0:1]

PPC_A[14:31]

A[14:31]

MPI_CLK

CLKOUT

RD/

MPI_RW

DP[0:m]

1, 2, 4

8, 16, 32

DP[0:m]

D[0:n]

CS1

MPI_TEA

TEA

MPI_BURST

BURST

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