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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LFSC датащи(PDF) 74 Page - Lattice Semiconductor |
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LFSC датащи(HTML) 74 Page - Lattice Semiconductor |
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74 / 237 page  3-30 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet Switching Test Conditions Figure 3-15 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-4. Figure 3-15. Output Test Load, LVTTL and LVCMOS Standards Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces Test Condition CL Timing Ref. VT LVTTL and other LVCMOS settings (L -> H, H -> L) 30pF LVCMOS 3.3 = 1.5V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — LVCMOS 2.5 I/O (Z -> H) 30pF VCCIO/2 VOL LVCMOS 2.5 I/O (Z -> L) VCCIO/2 VOH LVCMOS 2.5 I/O (H -> Z) VOH - 0.15 VOL LVCMOS 2.5 I/O (L -> Z) VOL + 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. DUT CL Test Poi nt |
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