LFSC datasheet(26/237 Pages) LATTICE

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2-22

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of

three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived

directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with

the buffer (for open drain emulation). Figure 2-24 shows the diagram of the Tristate Register Block.

Tristate SDR Register/Latch Block

The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable

options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set

Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control

MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be

disabled on a PIO basis.

Tristate DDR/Shift Register Block

The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the

associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data

from the FPGA fabric to provide a high-speed tri-state control stream.

There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate sig-

nal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ

cycle when the FPGA is receiving data, the parallel terminations are turned on.

Figure 2-24. Tristate Register Block

I/O Architecture Rules

Table 2-6 shows the PIO usage for x1, x2, x4 gearing. The checkmarks in the columns show the speciﬁc PIOs that

are used for each gearing mode. When using x2 or x4 gearing, any PIO which is not used for gearing can still be

used as an output.

DDR/Shift Register Block2

•

DDR

• DDR + half clock

HCLKOUT

LCLKOUT

From

Routing

(To PURESPEED

I/O Buffer)

From

Control

MUX

From Output

OPOS1

VCC

GND

ONEG1

Notes:

1. CE, Update, Set and Reset not shown for clarity.

2. DDR/Shift Register Block shared with output register block.

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