LFSC datasheet(38/237 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

VDDAX25 needs to be connected independent of the use of the SERDES. This supply is used to control the SER-

DES CML I/O regardless of the SERDES being used in the design.

Supported Source Synchronous Interfaces

The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify

the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR stan-

dards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet.

Table 2-11. Source Synchronous Standards Table

ﬂexiPCS™ (Physical Coding Sublayer Block)

ﬂexiPCS Functionality

The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded

RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded SER-

DES with associated Physical Coding Sublayer (PCS) logic. The ﬂexiPCS logic can be conﬁgured to support

numerous industry standard high-speed data transfer protocols.

Each channel of ﬂexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial

data transfers at data rates up to 3.8 Gbps. The PCS logic in each channel can be conﬁgured to support an array of

popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or

above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X speciﬁcation), 1.02 or 2.04 Gbps Fibre Channel,

PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a num-

ber of conﬁgurations to allow users ﬂexibility in designing their own high-speed data interface.

Protocols requiring data rates above 3.8 Gbps can be accommodated by dedicating either one pair or all four chan-

nels in one ﬂexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data

rates up to 15.2 Gbps. A single ﬂexiPCS quad can be conﬁgured to support 10Gb Ethernet (with a fully compliant

XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO.

The ﬂexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the

FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each

SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down

to DC rates on the same SERDES pin, as required by some Serial Digital Video applications.

The ispLEVER design tools from Lattice support all modes of the ﬂexiPCS. Most modes are dedicated to applica-

tions associated with a speciﬁc industry standard data protocol. Other more general purpose modes allow a user to

Source Synchronous Standard

Clocking

Speeds (MHz)

Data Rate (Mbps)

RapidIO

DDR

500

1000

HyperTransport

DDR

800

1600

SPI4.2 (POS-PHY4)/NPSI

DDR

500

1000

SFI4/XSBI

DDR

SDR

334

667

XGMII

DDR

156.25

312

CSIX

SDR

250

QDRII/QDRII+ memory interface

DDR

300

600

DDR memory interface

DDR

240

480

DDRII memory interface

DDR

333

667

RLDRAM memory interface

DDR

400

800

1. Memory width is dependent on the system design and limited by the number of I/Os in the device.

2. Tested using non-coupled, six-inch traces fed directly into an edge clock resource.

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