LFSC datasheet(78/237 Pages) LATTICE

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Pinout Information

Lattice Semiconductor

LatticeSC/M Family Data Sheet

D[n:0]

I/O

In parallel conﬁguration modes, D[7:0] receives conﬁguration data,

and each pin is pull-up enabled. For slave serial mode, D0 is the data

input.

D[7:3] is the output internal status for peripheral mode when RDN is

low.

D[7:0] is also the ﬁrst byte of MPI data pins.

In MPI conﬁguration mode, MPI selectable data bus width from 8 and

16-bit. Driven by a bus master in a write transaction. Driven by MPI in

a read transaction.

DP[m:0]

I/O

MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for

D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16].

BUSYN/RCLK/SCK

During conﬁguration in peripheral mode, high on BUSYN indicates

another byte can be written to the FPGA. If a read operation is done

when the device is selected, the same status is also available on D[7]

in asynchronous peripheral mode.

During conﬁguration in slave parallel mode, low on BUSYN inhibits the

external host from sending new data. The output is used by slave par-

allel and master serial modes only for decompression.

During conﬁguration in master parallel and master byte modes, RCLK

is a read clock output signal to an external memory. The RCLK fre-

quency is the same as CCLK when used with uncompressed bit-

streams. RCLK will be 1/8 the frequency of CCLK when the bitstream

is compressed.

During conﬁguration in SPI modes, SCK is generated by the device

and connected to the CLK input of the FLASH memory.

MPI Interface (Dedicated pin)

MPI_IRQ_N

MPI Interrupt request active low signal is controlled by system bus

interrupt controller and may be sourced from any bus error or MPI con-

ﬁguration error. It can be connected to one of MPC860 IRQ pins.

MPI Interface (User I/O if MPI is not used.)

MPI_CS0N MPI_CS1

MPI chip select pins, active low on MPI_CS0N while active high on

MPI_CS1. Both have to be active during the whole transfer data

phase. During transfer address phase, both can be inactive so that the

decoding for them from address can be slow. If they are active during

address phase, one cycle can be saved for sync read.

MPI_CLK

This is the PowerPC bus clock. It can be a source of the clock for

embedded system bus. If MPI_CLK is used as system bus clock, MPI

will be set into sync mode by default. All of the operation on PowerPC

side of MPI are synchronized to the rising edge of this clock.

MPI_TSIZ[1:0]

Driven by a bus master to indicate the data transfer size for the trans-

action. 01 for byte, 10 for half-word, and 00 for word.

MPI_WR_N

Driven high indicates that a read access is in progress. Driven low

indicates that a write access is in process.

MPI_BURST

Driven active low indicates that a burst transfer is in progress. Driven

high indicates that the current transfer is not a burst.

MPI_BDIP

Active low “Burst Data in Process” is driven by a PowerPC processor.

Asserted indicates that the second beat in front of the current one is

requested by the master. Negated before the burst transfer ends to

abort the burst data phase.

Signal Descriptions (Cont.)

Signal Name

I/O

Description

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