PSD835G2 datasheet(43/102 Pages) STMICROELECTRONICS

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PSD835G2

Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con-

nected to Port A pins and are named as McellA0-

McellA7. The other eight macrocells are connect-

ed to Port B pins and are named as McellB0-

McellB7.

The Output Macrocell (OMC) architecture is

shown in Figure 16., page 45. As shown in the fig-

ure, there are native product terms available from

the AND Array, and borrowed product terms avail-

able (if unused) from other Output Macrocells

(OMC). The polarity of the product term is con-

trolled by the XOR gate. The Output Macrocell

(OMC) can implement either sequential logic, us-

ing the flip-flop element, or combinatorial logic.

The multiplexer selects between the sequential or

combinatorial logic outputs. The multiplexer output

can drive a port pin and has a feedback path to the

AND Array inputs.

The flip-flop in the Output Macrocell (OMC) block

can be configured as a D, T, JK, or SR type in the

PSDsoft program. The flip-flop’s clock, preset, and

clear inputs may be driven from a product term of

the AND Array. Alternatively, CLKIN (PD1) can be

used for the clock input to the flip-flop. The flip-flop

is clocked to the rising edge of CLKIN (PD1). The

preset and clear are active High inputs. Each clear

input can use up to two product terms.

Table 31. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

Port

Assignment

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellA0

Port A0

McellA1

Port A1

McellA2

Port A2

McellA3

Port A3

McellA4

Port A4

McellA5

Port A5

McellA6

Port A6

McellA7

Port A7

McellB0

Port B0

McellB1

Port B1

McellB2

Port B2

McellB3

Port B3

McellB4

Port B4

McellB5

Port B5

McellB6

Port B6

McellB7

Port B7

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