PSD835G2 datasheet(35/102 Pages) STMICROELECTRONICS

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PSD835G2

SECTOR SELECT AND SRAM SELECT

Sector Select (FS0-FS7 for primary Flash memo-

ry, CSBOOT0-CSBOOT3 for secondary Flash

memory) and SRAM Select (RS0) are all outputs

of the DPLD. They are setup using PSDsoft. The

following rules apply to the equations for these sig-

nals:

Primary Flash memory and secondary Flash

memory Sector Select signals must not be

larger than the physical sector size.

Any primary Flash memory sector must not be

mapped in the same memory space as

another primary Flash memory sector.

A secondary Flash memory sector must not be

mapped in the same memory space as

another secondary Flash memory sector.

SRAM and I/O spaces must not overlap.

A secondary Flash memory sector may

overlap a primary Flash memory sector. In

case of overlap, priority is given to the

secondary Flash memory sector.

SRAM and I/O spaces may overlap any other

memory sector. Priority is given to the SRAM

and I/O.

Example

FS0 is valid when the address is in the range of

8000h to BFFFh, CSBOOT0 is valid from 8000h to

9FFFh, and RS0 is valid from 8000h to 87FFh.

Any address in the range of RS0 always accesses

the SRAM. Any address in the range of CSBOOT0

greater than 87FFh (and less than 9FFFh) auto-

matically addresses secondary Flash memory

segment 0. Any address greater than 9FFFh ac-

cesses the primary Flash memory segment 0. You

can see that half of the primary Flash memory seg-

ment 0 and one-fourth of secondary Flash memory

segment 0 cannot be accessed in this example.

Also note that an equation that defined FS1 to any-

where in the range of 8000h to BFFFh would not

be valid.

Figure 9 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

level 3 has the lowest.

Memory Select Configuration for MCUs with

Separate Program and Data Spaces

The 80C51 and compatible family of MCUs have

separate address spaces for Program memory

(selected using Program Select Enable (PSEN,

CNTL2)) and Data memory (selected using Read

Strobe (RD, CNTL1)). Any of the memories within

the PSD can reside in either space or both spaces.

This is controlled through manipulation of the VM

The VM register is set using PSDsoft to have an

initial value. It can subsequently be changed by

the MCU so that memory mapping can be

changed on-the-fly.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the primary and

secondary Flash memories. This is easily done

with the VM register by using PSDsoft to configure

it for Boot-up and having the MCU change it when

desired.

Table 24., page 23 describes the VM Register.

Figure 9. Priority Level of Memory and I/O

Components

Level 1

SRAM, I /O, or

Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

AI02867D

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