PSD835G2 datasheet(28/102 Pages) STMICROELECTRONICS

28 / 102 page

PSD835G2

28/102

INSTRUCTIONS

An instruction consists of a sequence of specific

operations. Each received Byte is sequentially de-

coded by the PSD and not executed as a standard

WRITE operation. The instruction is executed

when the correct number of Bytes is properly re-

ceived and the time between two consecutive

Bytes is shorter than the time-out period. Some in-

structions are structured to include READ opera-

tions after the initial WRITE operations.

The instruction must be followed exactly. Any in-

valid combination of instruction Bytes or time-out

between two consecutive bytes while addressing

Flash memory resets the device logic into READ

mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in

Table 28., page 27:

Flash memory:

■

Erase memory by chip or sector

■

Suspend or resume sector erase

■

Program a Byte

■

Reset to READ mode

■

Read primary Flash Identifier value

■

Read Sector Protection Status

■

Bypass

These instructions are detailed in Table 28. For ef-

ficient decoding of the instructions, the first two

Bytes of an instruction are the coded cycles and

are followed by an instruction Byte or a confirma-

tion Byte. The coded cycles consist in writing the

data AAh to address X555h during the first cycle

and data 55h to address XAAAh during the second

cycle unless the Bypass Instruction feature is

used). Address signals A15-A12 are Don’t Care

during the instruction WRITE cycles. However, the

appropriate

Sector

Select

(FS0-FS7

CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have

the same instruction set (except for Read Primary

Flash Identifier). The Sector Select signals deter-

mine which Flash memory is to receive and exe-

cute the instruction. The primary Flash memory is

selected if any one of Sector Select (FS0-FS7) is

High, and the secondary Flash memory is selected

any

one

Sector

Select

(CSBOOT0-

CSBOOT3) is High.

Power-up Mode

The PSD internal logic is reset upon Power-up to

the READ mode. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must be held Low, and

Write Strobe (WR, CNTL0) High, during Power-up

for maximum security of the data contents and to

remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

WRITE cycle initiation is locked when VCC is be-

low VLKO.

READ

Under typical conditions, the MCU may read the

primary Flash memory or the secondary Flash

memory using READ operations just as it would a

ROM or RAM device. Alternately, the MCU may

use READ operations to obtain status information

about a Program or Erase cycle that is currently in

progress. Lastly, the MCU may use instructions to

read special data from these memory blocks. The

following sections describe these READ functions.

Read Memory Contents

Primary Flash memory and secondary Flash

memory are placed in the READ mode after Pow-

er-up, chip reset, or a Reset Flash instruction (see

Table 28). The MCU can read the memory con-

tents of the primary Flash memory or the second-

ary Flash memory by using READ operations any

time the READ operation is not part of an instruc-

tion.

Read Primary Flash Identifier

The primary Flash memory identifier is read with

an instruction composed of 4 operations: 3 specific

WRITE operations and a READ operation (see Ta-

ble 28., page 27). The identifier for the device is

E8h.

Read Memory Sector Protection Status

The primary Flash memory Sector Protection Sta-

tus is read with an instruction composed of 4 oper-

ations: 3 specific WRITE operations and a READ

operation (see Table 28). The READ operation

produces 01h if the Flash memory sector is pro-

tected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks

(primary Flash memory or secondary Flash mem-

ory) can also be read by the MCU accessing the

Flash Protection and Flash Boot Protection regis-

ters in PSD I/O space. See Flash Memory Sector

Protect, page 34 for register definitions.

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