PSD835G2 datasheet(23/102 Pages) STMICROELECTRONICS

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PSD835G2

Table 24. VM Register

Note: 1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset.

Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.

2. Bit Definitions:

SR_code0 = PSEN cannot access SRAM in 80C51XA modes.

1 = PSEN can access SRAM in 80C51XA modes.

Boot_code0 = PSEN cannot access Secondary NVM in 80C51XA modes.

1 = PSEN can access Secondary NVM in 80C51XA modes.

FL_code0 = PSEN cannot access Primary Flash memory in 80C51XA modes.

1 = PSEN can access Primary Flash memory in 80C51XA modes.

Boot_data0 = RD cannot access Secondary NVM in 80C51XA modes.

1 = RD can access Secondary NVM in 80C51XA modes.

FL_data0 = RD cannot access Primary Flash memory in 80C51XA modes.

1 = RD can access Primary Flash memory in 80C51XA modes.

Peripheral mode0 = Peripheral mode of Port F is disabled.

1 = Peripheral mode of Port F is enabled.

Table 25. Memory_ID0 Register

Note: Bit Definitions:

F_size[3:0]

4h = Primary Flash memory size is 4 Mbit

5h = Primary Flash memory size is 8Mbit

S_size[3:0]

0h = There is no SRAM

1h = SRAM size is 16 Kbit

3h = SRAM size is 64 Kbit

Table 26. Memory_ID1 Register

Note: Bit Definitions:

B_size[3:0]

0h = There is no Secondary NVM

2h = Secondary NVM size is 256 Kbit

B_type[1:0]

0h = Secondary NVM is Flash memory

1h = Secondary NVM is EEPROM

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

Peripheral

mode

not used

(set to ’0’)

not used

(set to ’0’)

FL_data

Boot_data

FL_code

Boot_code

SR_code

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

S_size 3

S_size 2

S_size 1

S_size 0

F_size 3

F_size 2

F_size 1

F_size 0

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

not used

(set to ’0’)

not used

(set to ’0’)

B_type 1

B_type 0

B_size 3

B_size 2

B_size 1

B_size 0

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