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PSD835G2 датащи(PDF) 86 Page - STMicroelectronics

номер детали PSD835G2
подробное описание детали  Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  102 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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PSD835G2 датащи(HTML) 86 Page - STMicroelectronics

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Table 59. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on Ports C and F.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Table 60. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol
Parameter
Conditions
-70
-90
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
fMAX
Maximum Frequency
External Feedback
1/(tS+tCO)
34.4
30.30
MHz
Maximum Frequency
Internal Feedback (fCNT)
1/(tS+tCO–10)
52.6
43.48
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
83.3
50.00
MHz
tS
Input Setup Time
14
15
+ 2
+ 12
ns
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
6
10
ns
tCL
Clock Low Time
Clock Input
6
10
ns
tCO
Clock to Output Delay
Clock Input
15
18
– 2
ns
tARD
CPLD Array Delay
Any macrocell
11
16
+ 2
ns
tMIN
Minimum Clock Period 2
tCH+tCL
12
20
ns
Symbol
Parameter
Conditions
-70
-90
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Min
Max
Min
Max
fMAXA
Maximum
Frequency
External Feedback
1/(tSA+tCOA)
38.4
26.32
MHz
Maximum
Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
MHz
Maximum
Frequency
Pipelined Data
1/(tCHA+tCLA)
47.6
37.3
MHz
tSA
Input Setup Time
6
8
+ 2
+ 12
ns
tHA
Input Hold Time
7
12
ns
tCHA
Clock Input High
Time
912
+ 12
ns
tCLA
Clock Input Low
Time
12
15
+ 12
ns
tCOA
Clock to Output
Delay
21
30
+ 12
– 2
ns
tARDA
CPLD Array Delay
Any macrocell
11
16
+ 2
ns
tMINA
Minimum Clock
Period
1/fCNTA
16
28
ns



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