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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD835G2 датащи(PDF) 37 Page - STMicroelectronics |
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PSD835G2 датащи(HTML) 37 Page - STMicroelectronics |
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37 / 102 page  37/102 PSD835G2 PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Note AN1154. Figure 12 shows the Page Register. The eight flip- flops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 12. Page Register MEMORY ID REGISTERS The 8-bit Read-only Memory Status Registers are included in the CSIOP space. The user can deter- mine the memory configuration of the PSD device by reading the Memory ID0 and ID1 Registers. The contents of the registers are defined in Table 25., page 23 and Table 26., page 23. RESET D0 - D 7 R/W D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D1 D2 D3 D4 D5 D6 D7 PAGE REGISTER PGR0 PGR1 PGR2 PGR3 DPLD AND CPLD INTERNAL SELECTS AND LOGIC PLD PGR4 PGR5 PGR6 PGR7 AI02871B |
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