PSD835G2 datasheet(57/102 Pages) STMICROELECTRONICS

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PSD835G2

80C51XA

The Philips 80C51XA MCU family supports an 8-

or 16-bit multiplexed bus that can have burst cy-

cles. Address bits (A3-A0) are not multiplexed,

while (A19-A4) are multiplexed with data bits

(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)

are multiplexed with data bits (D7-D0).

The 80C51XA can be configured to operate in

eight-bit data mode (as shown in Figure 24).

The 80C51XA improves bus throughput and per-

formance by executing burst cycles for code fetch-

es. In Burst Mode, address A19-A4 are latched

internally by the PSD, while the 80C51XA changes

the A3-A0 signals to fetch up to 16 bytes of code.

The PSD access time is then measured from ad-

dress A3-A0 valid to data in valid. The PSD bus

timing requirement in Burst Mode is identical to the

normal bus cycle, except the address setup and

hold time with respect to Address Strobe (ALE/AS,

PD0) does not apply.

Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus

EA/WAIT

XTAL1

XTAL2

RESET

RXD0

TXD0

RXD1

TXD1

T2EX

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PA0

PA2

PA1

PA3

PA4

PA5

PA6

PA7

A12D8

A13D9

A14D10

A15D11

A16D12

A17D13

A18D14

A19D15

ADIO0(2)

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CNTL0 (WR)

CNTL1(RD)

CNTL2 (PSEN)

PD3

PD1 (CLKIN)

PD2 (CS)

RESET

WRL

PSEN

ALE

RESET

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

PSD

80C31

A10

A11

A12

A13

A14

A15

ALE

A[3:0]

RESET

AI02883D

CRYSTAL

A[19:12] D[7:0]

PD0 (ALE)

PE2 (TDI)

PE0 (TMS)

PE1 (TCK/ST)

PE5 (TERR)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE7 (VBATON)

PE6 (VSTBY)

VCC

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC2

PC1

PC3

PC4

PC5

PC6

PC7

GND GND GND GND GND

PSEN

929

INT0

INT1

VCC

A0/WRH

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