PSD835G2 datasheet(38/102 Pages) STMICROELECTRONICS

38 / 102 page

PSD835G2

38/102

PLDS

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

in PSDsoft, the logic is programmed into the de-

vice and available upon Power-up.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and

detail

Decode

PLD

(DPLD), page 40

and

Complex

PLD

(CPLD), page 41. Figure 13 shows the configura-

tion of the PLDs.

The DPLD performs address decoding for Select

signals for internal components, such as memory,

registers, and I/O ports.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

used to generate External Chip Select (ECS0-

ECS2) signals.

The AND Array is used to form product terms.

These product terms are specified using PSDsoft.

An Input Bus consisting of 82 signals is connected

to the PLDs. The signals are shown in Table 30.

The Turbo Bit in PSD

The PLDs in the PSD can minimize power con-

sumption by switching to standby when inputs re-

main unchanged for an extended time of about

70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of

PMMR0) automatically places the PLDs into

standby if no inputs are changing. Turning the Tur-

bo mode off increases propagation delays while

reducing

power

consumption.

See

POWER

MANAGEMENT, page 70, on how to set the Tur-

bo Bit.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

Table 30. DPLD and CPLD Inputs

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

Input Source

Input Name

Number

Signals

MCU Address Bus1

A15-A0

MCU Control Signals

CNTL2-CNTL0

Reset

RST

Power-down

PDN

Port A Input

Macrocells

PA7-PA0

Port B Input

Macrocells

PB7-PB0

Port C Input

Macrocells

PC7-PC0

Port D Inputs

PD3-PD0

Port F Inputs

PF7-PF0

Page Register

PGR7-PGR0

Macrocell A Feedback

MCELLA.FB7-FB0

Macrocell B Feedback

MCELLB.FB7-FB0

Secondary Flash

memory Program

Status Bit

Ready/Busy

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