PSD835G2 datasheet(84/102 Pages) STMICROELECTRONICS

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PSD835G2

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Table 57. DC Characteristics

Note: 1. Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.

2. CSI deselected or internal Power-down mode is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 34 for the PLD current calculation.

5. IOUT = 0mA

Symbol

Parameter

Test Condition

(in addition to those in

Table 52., page 82)

Min.

Typ.

Max.

Unit

VIH

Input High Voltage

4.5V < VCC < 5.5V

VCC +0.5

VIL

Input Low Voltage

4.5V < VCC < 5.5V

–0.5

0.8

VIH1

Reset High Level Input Voltage

(Note 1)

0.8VCC

VCC + 0.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–0.5

0.2VCC –0.1

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC (min) for Flash Erase and

Program

2.5

4.2

VOL

Output Low Voltage

IOL = 20µA, VCC = 4.5V

0.01

0.1

IOL = 8mA, VCC = 4.5V

0.25

0.45

VOH

Output High Voltage Except

VSTBY On

IOH = –20µA, VCC = 4.5V

4.4

4.49

IOH = –2mA, VCC = 4.5V

2.4

3.9

VOH1

Output High Voltage VSTBY On

IOH1 = –1µA

VSTBY – 0.8

VSTBY

SRAM Stand-by Voltage

2.0

VCC

ISTBY

SRAM Stand-by Current

VCC = 0V

0.5

µA

IIDLE

Idle Current (VSTBY input)

VCC > VSTBY

–0.1

0.1

µA

VDF

SRAM Data Retention Voltage

Only on VSTBY

ISB

Stand-by Supply Current

for Power-down Mode

CSI > VCC – 0.3V

(Notes 2,3,5)

100

200

µA

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±0.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

±5

µA

ICC (DC)

(Note5)

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0 MHz (Note 3)

µA/PT

PLD_TURBO = On,

f = 0 MHz

400

700

µA/PT

Flash memory

During Flash memory

WRITE/Erase Only

Read only, f = 0 MHz

SRAM

f = 0 MHz

ICC (AC)

(Note5)

PLD AC Base

Figure 34

(note4)

Flash memory AC Adder

2.5

3.5

mA/

MHz

SRAM AC Adder

1.5

3.0

mA/

MHz

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