PSD835G2 datasheet(16/102 Pages) STMICROELECTRONICS

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PSD835G2

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PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional

blocks. Figure 3., page 15 shows the architecture

of the PSD device family. The functions of each

block are described briefly in the following sec-

tions. Many of the blocks perform multiple func-

tions and are user configurable.

Memory

Each of the memory blocks is briefly discussed in

the following paragraphs. A more detailed discus-

sion can be found in the section entitled Memory

Blocks, page 24. The 4 Mbit (512K x 8) Flash

memory is the primary memory of the PSD. It is di-

vided into 8 equally-sized sectors that are individ-

ually selectable.

The 256 Kbit (32K x 8) secondary Flash memory

is divided into 4 equally-sized sectors. Each sector

is individually selectable.

The 64 Kbit SRAM is intended for use as a

scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to

Voltage Standby (VSTBY, PC2), data is retained in

the event of power failure.

Each sector of memory can be located in a differ-

ent address space as defined by the user. The ac-

cess times for all memory types includes the

address latching and DPLD decoding time.

Page Register

The 8-bit Page Register expands the address

range of the MCU by up to 256 times. The paged

address can be used as part of the address space

to access external memory and peripherals, or in-

ternal memory and I/O. The Page Register can

also be used to change the address mapping of

sectors of the Flash memories into different mem-

ory spaces for IAP.

PLDs

The device contains two PLDs, the Decode PLD

(DPLD) and the Complex PLD (CPLD), as shown

in Table 2, each optimized for a different function.

The functional partitioning of the PLDs reduces

power consumption, optimizes cost/performance,

and eases design entry.

The DPLD is used to decode addresses and to

generate Sector Select signals for the PSD inter-

nal memory and registers. The CPLD can imple-

ment user-defined logic functions. The DPLD has

combinatorial outputs. The CPLD has 16 Output

Macrocells (OMC) and 8 combinatorial outputs.

The PSD also has 24 Input Macrocells (IMC) that

can be configured as inputs to the PLDs. The

PLDs receive their inputs from the PLD Input Bus

and are differentiated by their output destinations,

number of product terms, and macrocells.

The PLDs consume minimal power by using Pow-

er-Management design techniques. The speed

and power consumption of the PLD is controlled

by the Turbo Bit in PMMR0 and other bits in the

PMMR2. These registers are set by the MCU at

run-time. There is a slight penalty to PLD propaga-

tion time when invoking the power management

features.

I/O Ports

The PSD has 52 I/O pins distributed over the sev-

en ports (Port A, B, C, D, E, F and G). Each I/O pin

can be individually configured for different func-

tions. Ports can be configured as standard MCU I/

O ports, PLD I/O, or latched address outputs for

MCUs using multiplexed address/data buses.

The JTAG pins can be enabled on Port E for In-

System Programming (ISP). Ports F and G can

also be configured as data ports for a non-multi-

plexed bus.

Ports A and B can also be configured as a data

port for a non-multiplexed bus.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that

have either multiplexed or non-multiplexed ad-

dress/data buses. The device is configured to re-

spond to the MCU’s control signals, which are also

used as inputs to the PLDs. For examples, please

see MCU Bus Interface Examples, page 52.

Table 2. PLD I/O

Table 3. JTAG SIgnals on Port E

Name

Inputs

Outputs

Product

Terms

Decode PLD (DPLD)

Complex PLD (CPLD)

150

Port E Pins

JTAG Signal

PE0

TMS

PE1

TCK

PE2

TDI

PE3

TDO

PE4

TSTAT

PE5

TERR

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